The development of semiconductor switching technology for high power applications in motor drive circuits, appliance controls and lighting ballasts, for example, began with the bipolar junction transistor. As the technology matured, bipolar devices became capable of handling large current densities in the range of 40-50 A/cm.sup.2, with blocking voltages of 600 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to the suitability of bipolar transistors for all high power applications. First of all, bipolar transistors are current controlled devices. For example, a large control current into the base, typically one fifth to one tenth of the collector current, is required to maintain the device in an operating mode. Even larger base currents, however, are required for high speed forced turn-off. These characteristics make the base drive circuitry complex and expensive. The bipolar transistor is also vulnerable to breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications, for example. Furthermore, it is difficult to parallel connect these devices since current diversion to a single device may occur at high temperatures, making emitter ballasting schemes necessary.
The power MOSFET was developed to address this base drive problem. In a power MOSFET, a gate electrode bias is applied for turn-on and turn-off control. Turn-on occurs when a conductive channel is formed between the MOSFET's source and drain regions under appropriate bias. The gate electrode is separated from the device's active area by an intervening insulator, typically silicon dioxide. Because the gate is insulated from the active area, little if any gate current is required in either the on-state or off-state. The gate current is also kept small during switching because the gate forms a capacitor with the device's active area. Thus, only charging and discharging current ("displacement current") is required. The high input impedance of the gate, caused by the presence of a gate insulator, is a primary feature of the power MOSFET. Moreover, because of the minimal current demands on the gate, the gate drive circuitry and devices can be easily implemented on a single chip. As compared to bipolar technology, the simple gate control provides for a large reduction in cost and a significant improvement in reliability.
These benefits are offset, to some extent, by the high on30 resistance of the MOSFET's active region, which arises from the absence of minority carrier injection. As a result, the device's operating forward current density is limited to relatively low values, typically in the range of 10 A/cm.sup.2, for a 600 V device, as compared to 40-50 A/cm.sup.2 for the bipolar transistor.
On the basis of these features of power bipolar transistors and MOSFET devices, hybrid devices embodying a combination of bipolar current conduction with MOS-controlled current flow were developed and found to provide significant advantages over single technologies such as bipolar or MOSFET alone. Classes of such hybrid devices include various types of MOS-gated thyristors as well as the insulated gate bipolar transistor (IGBT), also commonly referred to by the acronyms COMFET (Conductivity-Modulated FET) and BIFET (Bipolar-mode MOSFET).
Examples of insulated gate bipolar transistors are described in U.S. Pat. Nos. 5,160,985 and 5,170,239 and in U.S. Pat. No. 5,273,917 to Sakurai; U.S. Pat. No. 5,331,184 to Kuwahara; U.S. Pat. No. 5,360,984 to Kirihata; U.S. Pat. Nos. 5,396,087 and 5,412,228 to B. J. Baliga; U.S. Pat. No. 5,485,022 to Matsuda; U.S. Pat. No. 5,485,023 to Sumida; U.S. Pat. No. 5,488,236 to Baliga et al.; and U.S. Pat. No. 5,508,534 to Nakamura et al. In particular, U.S. Pat. No. 5,360,984 to Kirihata discloses a semiconductor substrate containing an IGBT therein and a freewheeling/flyback diode for, among other things, bypassing parasitic reverse voltage surges which are typical in inductive power circuit applications. However, the antiparallel-connected freewheeling diode disclosed by Kirihata increases the area occupied by the IGBT and may cause an unnecessary stray inductance due to the wiring which interconnects the IGBT with the freewheeling diode. Moreover, the IGBT of Kirihata may be susceptible to sustained parasitic thyristor latch-up.
As will be understood by those skilled in the art, the parasitic thyristor latch-up phenomenon serves as a main factor in limiting the amount of gate-controllable forward current an IGBT cell can handle. FIG. 1 illustrates a layout schematic of a conventional n-channel IGBT cell and FIG. 2 illustrates a cross-sectional view of the IGBT of FIG. 1, taken along line 2--2'. Referring now to FIGS. 1 and 2, an N.sup.+ -type buffer layer 12 is formed on a major surface of a P.sup.+ -type collector layer 10 (e.g., P.sup.+ -type semiconductor substrate). An N.sup.- -type epitaxial layer 14 is formed on a surface of the N.sup.+ -type buffer layer 12 and forms a non-rectifying junction therewith. A P-type well region or base region is partially formed in the surface of the N.sup.- -type epitaxial layer 14 by selectively diffusing a P-type impurity into the epitaxial layer 14. As illustrated, the P-type well region is formed by a shallow P-type well region 16 having a relatively low P-type impurity concentration therein and a deep P-type well region 18 (e.g., contact region) having a relatively high impurity concentration therein. The deep P-type well region 18 is provided in a central portion of the shallow P-type well region 16. An N.sup.+ -type emitter region 20 may also be formed at the surface of the P-type well region by selectively diffusing N-type impurities therein.
A gate insulating film 22 is formed on the surface of the P-type well region, as illustrated. A gate electrode 24 is also formed on the gate insulating film 22, and a conductive emitter electrode 27 is formed in electrical contact with the N.sup.+ -type emitter region 20 and P-type well region. A conductive collector electrode (not shown) may also be formed on the P.sup.+ -type collector layer 10. In this IGBT device, the gate insulating film 22 and gate electrode 24 form a MOS insulated gate electrode which extends opposite a portion of the P-type well region that extends between the N.sup.- -type epitaxial layer 14 and the N.sup.+ -type emitter region 20 (i.e., the "channel" region). As will be understood by those skilled in the art, a positive voltage may be applied to the gate electrode 24 to cause the formation of a low resistance inversion-layer channel in the channel region. During forward on-state conduction, this inversion layer channel provides a highly conductive path for electrons to travel from the emitter region 20 to the epitaxial layer 14. Symbol I.sub.e of FIG. 2 indicates the direction of flow of the electron current.
During forward on-state conduction, positive holes are also injected from the P.sup.+ -type collector layer 10 into the N.sup.- -type epitaxial layer 14 as minority carriers. A portion of these holes recombine with the electrons that pass through the channel region and enter the epitaxial layer 14, however the remaining holes are collected by the P-type well region as hole current I.sub.h. Thus, the IGBT basically operates like a conventional bipolar junction transistor, however, the conductivity of the N.sup.- -type epitaxial layer 14 (i.e., floating base region) can be increased due to a conductivity modulation effect. Thus, an IGBT can have lower on-state voltage drop and larger current carrying capacity than a conventional power MOS device.
Unfortunately, conventional IGBT devices typically include parasitic PNPN thyristor structures therein. This parasitic thyristor structure may be formed by two regeneratively cross-coupled bipolar junction transistors. Here, for example, an NPN bipolar junction transistor may be defined by the N.sup.- -type epitaxial layer 14, the P-type well region and the N.sup.+ -type emitter region 20 and a PNP bipolar junction transistor may be defined by the P.sup.+ -type collector layer 10, the N.sup.- -type epitaxial layer 104 and the P-type well region. As will be understood by those skilled in the art, these cross-coupled bipolar junction transistors may latch-up and cause sustained parasitic conduction if the forward on-state current in the IGBT device become excessive. This sustained parasitic thyristor conduction may not be prevented by merely removing any on-state gate bias applied to the gate electrode 24.
Sustained parasitic conduction may occur if the P-N junction between the P-type well region 16 and N-type source region 20 becomes forward biased. Such forward biasing may occur if the amount of hole current I.sub.h flowing directly underneath the N.sup.+ -type emitter region 20 in a lateral direction exceeds a particular level and causes the voltage underneath the N-type emitter region 20 to increase to a level sufficient to forward bias the P-N junction and turn on the NPN bipolar junction transistor. Turn-on of the NPN bipolar junction transistor can also induce turn on of the PNP bipolar junction transistor in such a manner that a sustainable regenerative forward current is established through the IGBT device. If this regenerative forward current is excessive, the performance and lifetime of the IGBT device may be severely degraded.
Many attempts have been made to make IGBT devices less susceptible to parasitic thyristor latch-up. One such attempt includes the use of a highly doped central P+ well region 18 (e.g., contact region) so that the total lateral series resistance underneath the N-type source region 20 is maintained at a low level. If the series resistance is low enough, the P-N junction between the P-type well region and N-type source region 20 may not become forward biased during forward conduction. In order to form the highly doped P-type contact region 18 in FIG. 2, the P-type well region 16 must be deeply formed (for a high breakdown voltage device) and the P.sup.+ -type well region 18 must also be deeply formed. However, since the P.sup.+ -type well region 18 is typically formed by diffusion of P-type impurities from the surface, the concentrations of the P-type impurities fall off as the depth of the P-type well region is increased. Thus, the resistance of the P-type well region underneath the N-type source region 20 may not be sufficiently reduced. Moreover, increasing the concentration of P-type impurities in the P-type well region 16 may increase the concentration of P-type dopants in the channel region and such an increase may increase the threshold voltage of the MOS control transistor beyond an acceptable level.
Thus, notwithstanding these attempts to form IGBTs, there still continues to be a need for methods of forming highly integrated power semiconductor devices having reduced susceptibility to sustained parasitic thyristor latch-up.